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Board Components
Table 2–6. SSRAM Pin Table (Continued)
K9
E5
FPGA Pin
88
89
U74 Pin
Pin Function
GW_n
CLK
Board Net Name
ssram_gw_n
sram_clk
The following pins on U74 have fixed connections, which restricts the
usable modes of operation:
■
■
■
■
MODE is pulled low to enable Linear Burst
ZZ is pulled low to leave the chip enabled
GLOBALW_n is pulled high to disable the global write
CE2 and CE3_n are wired high and low respectively to be enabled
and to make CE1_n the master chip enable
f
DDR SDRAM
Chip (U63)
See www.cypress.com for detailed information about the SSRAM chip.
U63 is a Micron DDR SDRAM chip. Depending on the board revision, the
part number is MT46V16M16TG or MT46V16M16P-6T. The DDR
SDRAM pins are connected to the FPGA as shown in Table 2–7 . Altera
provides a DDR SDRAM controller that allows a Nios II processor to
access the DDR SDRAM device as a large, linearly-addressable memory.
Table 2–7. DDR SDRAM Pin Table
R2
R3
R4
P7
P6
T2
T3
R6
W2
W1
U6
U7
U5
Y1
FPGA Pin
2
4
5
7
8
10
11
13
54
56
57
59
60
62
U63 Pin
Board Net Name
sdram_dq0
sdram_dq1
sdram_dq2
sdram_dq3
sdram_dq4
sdram_dq5
sdram_dq6
sdram_dq7
sdram_dq8
sdram_dq9
sdram_dq10
sdram_dq11
sdram_dq12
sdram_dq13
Altera Corporation
May 2007
Reference Manual 2–9
Nios Development Board Cyclone II Edition
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